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Intel EPM570T144A5N — FPGA / CPLD & Programmable Logic

EPM570T144A5N MAX II CPLD, 440 sel makro, 5,4 ns

MPNEPM570T144A5N
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Altera MAX® II CPLD, EPM570T144A5N, 570 elemen logika, 440 sel makro, tpd 5,4 ns, 116 I/O, 144-LQFP, suplai internal 2,5V/3,3V, -40°C hingga 125°C.

$69.0000Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

EPM570T144A5N specifications
ParameterValue
SeriesMAX® II
MountingSurface Mount
Programmable typeIn System Programmable
Voltage supply - internal2.5V, 3.3V
Operating temperature-40°C~125°C(TJ)
PackageTray
Number of i (O)116
Case144-LQFP
Number of macrocells440
Delay time tpd(1) max5.4 ns
Number of logic elements (Blocks)570

Product details

MAX II CPLD – logika perekat (glue logic) instan-on dan berdaya rendah

Altera EPM570T144A5N adalah CPLD keluarga MAX® II dengan 570 elemen logika dan 440 sel makro dalam kemasan 144-LQFP. Penundaan propagasi 5,4 ns (tpd1) cukup cepat untuk decoding alamat, bridging bus, dan logika kontrol pada sistem yang tidak dapat mentolerir latensi boot-up FPGA. Arsitektur MAX II menggunakan fabrik look-up table (LUT) dengan konfigurasi flash non-volatile, sehingga saat dinyalakan ia langsung siap menggerakkan I/O dalam hitungan mikrodetik — tanpa memori konfigurasi eksternal.

tpd 5,4 ns – margin timing untuk jalur kombinatorial

Penundaan pin-ke-pin maksimum 5,4 ns (tpd1) menetapkan batas bawah kecepatan untuk logika registered dan kombinatorial.

Frequently asked questions

What is the difference between EPM570T144A5N and EPM570T144C5N?

The difference is the temperature grade. The EPM570T144A5N is rated for -40°C to 125°C (industrial/automotive), while the EPM570T144C5N is the commercial-temperature variant (0°C to 70°C). All other specs — logic elements, macrocells, I/O, speed grade, package — are identical.

How to program the EPM570T144A5N with Quartus II?

The EPM570T144A5N is supported in Intel Quartus II software (version 13.0sp1 or later). Use the MAX II device family selection, assign the 144-LQFP package, and program via the JTAG interface using a Byte Blaster II or USB-Blaster cable. The device is in-system programmable and retains configuration in on-chip flash.