440 macrocells at 5.4 ns — right-sizing the glue logic
The Intel EPM570T144C4N is a MAX® II CPLD with 440 macrocells and a 5.4 ns maximum propagation delay (tpd(1)). That delay figure means combinatorial decisions propagate from pin to pin in under 6 ns — fast enough to decode address lines, generate chip selects, or latch data without adding a wait state on a 100 MHz bus. With 116 I/O in a 144-LQFP (20x20 mm body), this part replaces a board full of 74-series logic or a handful of smaller PALs. The 570 logic elements back the macrocell count, giving you the fabric to absorb a few state machines alongside the decode logic.
Dual-voltage supply and instant-on operation
The I/O banks can be configured to match the voltage of the connected logic — no level translator needed for a 3.3 V flash or a 1.8 V SRAM interface. Being a CPLD, it is non-volatile and instant-on: the configuration is stored in flash cells on-chip, so the I/O pins assume their programmed state within microseconds of power reaching the VCC threshold. No external configuration memory, no boot time — the part is ready before the reset line on the attached processor de-asserts.
Active production — sourcing posture
The part is also available in tray packaging as listed.