What this is — and what it isn't
The TI ISO6760FQDWRQ1 is a six-channel, unidirectional SPI digital isolator in the ISO676x-Q1 family, built with capacitive coupling isolation technology. All six channels face Side 1.
AEC-Q100 — capable is not qualified
This part carries AEC-Q100 qualification.
Supply voltage — dual-range, not single-rail
The supply voltage is split: Side 1 runs 1.71V to 1.89V; Side 2 runs 2.25V to 5.5V.
Channel allocation — all six on one side
The ISO6760FQDWRQ1 puts all six channels as inputs on Side 1 (6/0 split). This is the right choice when the isolated barrier sits between a master SPI controller and a slave that never sends data back on the same isolator. If your application needs bidirectional SPI — MISO returning across the barrier — the ISO6761QDWRQ1 (5/1 split) or ISO6763QDWRQ1 (3/3 split) are pin-compatible siblings in the same package and qualification. The only difference is the channel direction allocation; all other specs (50 Mbps, 5000Vrms, 100 kV/µs CMTI, 18 ns propagation delay) are identical across the family.
The 16-SOIC wide-body (7.50 mm body width) is the standard footprint for high-isolation digital isolators. Pulse-width distortion is held to 7 ns max, and the 4.5 ns rise/fall times keep signal integrity clean on short PCB traces. Capacitive coupling means no magnetic core saturation concerns — the isolation barrier is purely dielectric, which matters for DC-correct SPI signals that must pass through without droop.