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Infineon Technologies CY28331OC-2 — Clock & Timing ICs

Infineon CY28331OC-2 Clock IC, 300MHz, 1:19 Fanout, 48-BSSOP

MPNCY28331OC-2
End of Life

Infineon Technologies CY28331OC-2 Clock & Timing IC, PLL Yes with Bypass, Fanout Distribution / Multiplexer / Spread Spectrum Clock Generator, 300 MHz max, 1:19 Input:Output, 48-BSSOP (0.295", 7.50mm Width), Surface Mount, Bulk.

$2.94Ref. price · indicative, final on quote
Packaging48-BSSOP (0.295", 7.50mm Width)
RoHSNot applicable
Sourced new & surplus through independent channelsAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY28331OC-2 specifications
ParameterValue
TypeFanout Distribution, Multiplexer, Spread Spectrum Clock Generator
MountingSurface Mount
Voltage3.135V ~ 3.465V
Frequency300MHz
Operating temperature0°C ~ 70°C
PLLYes with Bypass
InputCrystal
OutputClock
PackageBulk
Case48-BSSOP (0.295\", 7.50mm Width)
Divider (Multiplier)Yes/No
Number of circuits1
Ratio - Input:Output1:19
Differential - Input:OutputNo/Yes

Product details

Clock distribution hub with spread-spectrum control

The Infineon CY28331OC-2 is a three-in-one clock IC that combines fanout distribution, a multiplexer, and spread-spectrum clock generation in a single 48-BSSOP package. It accepts a crystal input and delivers up to 19 clock outputs at frequencies up to 300 MHz, with differential outputs available on the output side despite a single-ended input. The integrated PLL includes a bypass mode, allowing the system to switch between the internal synthesized clock and an external reference without glitches — useful during test, debug, or failover scenarios where the main PLL must be taken offline while the downstream logic keeps running.

What the 300 MHz ceiling and 1:19 ratio mean for your board

The 300 MHz maximum output frequency sets the upper speed limit for the entire clock tree. At this frequency, the differential outputs (No/Yes input-to-output) maintain signal integrity over longer PCB traces than single-ended routing would allow, reducing jitter accumulation across the 19 fanout paths. A single crystal drives 19 clock loads — the 1:19 input-to-output ratio means one timing source feeds the whole board, eliminating the need for multiple oscillators. The divider/multiplier block (Yes/No) lets you synthesize different frequencies from the same reference, though the part does not multiply the input frequency. The commercial temperature range (0°C to 70°C) limits deployment to controlled indoor environments — not suitable for industrial or automotive enclosures without active cooling.

Package and board-fit considerations

Housed in a 48-BSSOP package with a 0.295-inch (7.50 mm) body width, the CY28331OC-2 requires a surface-mount footprint with a 0.65 mm typical lead pitch. The supplier device package is listed as 48-SSOP, which is the same mechanical outline — confirm the land pattern matches the JEDEC MO-118 standard for SSOP-48 wide-body. Supplied in bulk tube packaging, not tape-and-reel — factor this into your pick-and-place setup if you are running high-volume assembly, as tube-fed feeders may need a changeover from the more common reel-fed lines.

Frequently asked questions

How can I order the CY28331OC-2 or check current availability?

The CY28331OC-2 is an active Infineon part sourced through independent distribution. No stock-holding claim is made on this page.

What does the PLL bypass feature do on the CY28331OC-2?

The PLL bypass mode lets the clock outputs switch to an external reference clock without the internal PLL running. This is useful for system test, low-frequency debug, or failover scenarios where the PLL must be disabled while the downstream logic continues to receive a clock signal.

What is the maximum frequency and how many outputs does the CY28331OC-2 support?

The device supports clock outputs up to 300 MHz and provides a 1:19 input-to-output ratio, meaning one crystal input drives 19 clock outputs. The outputs are differential, which improves signal integrity over longer PCB traces at high frequencies.