Package and footprint for layout
Housed in a 16-TSSOP package (4.40 mm wide), this part is a surface-mount fit for dense PCB layouts.
Lifecycle and sourcing reality
The CY26121ZXI-21 carries an active lifecycle status with ROHS3 compliance.
Cypress PacketClock™ CY26121ZXI-21 PLL clock generator, 33.33MHz max frequency, crystal input, 1:5 fanout, 3.135V–3.465V supply, -40°C to 85°C, 16-TSSOP surface mount.
$1.48Ref. price · indicative, final on quote
Packaging16-TSSOP (0.173", 4.40mm Width)
StockContact for availability
MOQ1 pcs
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Specifications
| Parameter | Value |
|---|---|
| Type | Clock Generator |
| Series | PacketClock™ |
| Mounting type | Surface Mount |
| Voltage | 3.135V ~ 3.465V |
| Frequency | 33.33MHz |
| Operating temperature | -40°C ~ 85°C (TA) |
| PLL | Yes |
| Input | Crystal |
| Output | Clock, Crystal |
| Package | Bulk |
| Case | 16-TSSOP (0.173\", 4.40mm Width) |
| Divider (Multiplier) | Yes/No |
| Number of circuits | 1 |
| Ratio - Input:Output | 1:5 |
| Differential - Input:Output | No/No |
Product details
Frequently asked questions
What is the equivalent to CY26121ZXI-21?
A functional peer is the CY2305SXI-1HT, which is a fanout buffer / zero-delay buffer also in a 1:5 ratio and -40°C to 85°C range, but it operates from a 3.0 V supply and does not include a divider/multiplier. Verify your input voltage and PLL configuration before substituting.
Can I use a 25 MHz crystal with CY26121ZXI-21?
The part accepts a crystal input, and the internal PLL can multiply to reach the 33.33 MHz maximum output. A 25 MHz crystal is within the typical operating range, but confirm the PLL multiplication ratio and output frequency do not exceed the 33.33 MHz limit.