25 MHz HCMOS clock at 3.3 V
The ASV2-25.000MHZ-C-L1-T: The ASV2-25.000MHZ-C--T is a standard crystal oscillator delivering a 25 MHz HCMOS clock rail at 3.3 V — a common MCU and FPGA reference frequency at the logic voltage these devices typically run on. HCMOS output swings rail-to-rail and可以直接驱动 standard logic inputs without a buffer, which keeps the BOM lean on clock-sensitive designs. The Enable/Disable pin lets the host shut down the oscillator for standby power savings — the disabled draw drops to 10 µA max versus 20 mA running, so a battery-backed node that gates the clock reference overnight will see a measurable idle current reduction.
±50 ppm stability across commercial temperature
Frequency stability is ±50 ppm over the operating range of -10°C to 70°C — the commercial temperature band typical of indoor instrumentation, consumer electronics, and factory-floor control boards. That stability covers USB Full-Speed timing budgets, standard UART clock references, and most SPI/UART microcontroller peripherals without needing trim. For anything requiring tighter timing — precision RTC, IEEE 1588, or serial interfaces with sub-0.1% error budgets — you would need a TCXO or OCXO instead, but for general-purpose logic-clock duty this is the correct spec to compare against your link budget. That low profile suits reflow-on-back-of-board or space-constrained daughter-card clock references where a taller HC-49S through-hole crystal would not fit. The no-lead pad geometry requires a moderate thermal pad at the PCB footprint centre — confirm your layout library has the correct paste mask, since some generic 7050 packages use a centre pad and some do not.
Active status and sourcing posture
No cross-reference or pin-compatible alternative is maintained in the ledger, so any second-source search defaults to parametric screening across the ASV2 family or equivalent 25 MHz HCMOS XO parts from the same manufacturer.