72 MHz MEMS clock in a 6-SMD footprint
The ASEMPC-72.000MHZ-T3: Base Resonator MEMS at confirms the construction; Output CMOS at tells you the drive format for the downstream PLL or FPGA clock input. Supply rail is 2.25-3.6V, drawing up to 35 mA when enabled and 26 mA disabled — the Enable/Disable pin at lets the clock stay on the BOM for a FPGA or SoC that gates its reference off during sleep modes without the overhead of a full oscillator power-cycle.
Stability and temperature grade
Frequency stability is ±50 ppm — that is the standard commercial-grade tolerance for a clock feeding a serializer, Ethernet PHY, or USB-PHY where the receiver's clock-data recovery tolerates the drift budget without a PLL correction path.
Package and layout fit
Confirm the landing pattern matches before substituting; not all half-size oscillators land on the same pad centre.