10-macrocell EE PLD, 10 ns tpd, 5 V only
The GAL22V10D-10LPI is a 10-macrocell electrically erasable PLD from Lattice's GAL®22V10 family, in a 24-pin DIP through-hole package. Propagation delay is 10 ns max, which sets the system clock ceiling — at 10 ns tpd the registered path from clock edge to output valid is tight enough for 50-80 MHz state machines in legacy 5 V backplanes.
Lattice Semiconductor lists the GAL22V10D-10LPI as obsolete. Because the part is EE (electrically erasable), unused inventory retains its programmed pattern through multiple erase/write cycles as long as the supply voltage stays within the 4.5-5.5 V window. No UV erasure window is needed — the die is in a standard 24-PDIP epoxy package.
24-DIP (0.300-inch row spacing, 7.62 mm) with through-hole leads — the footprint matches legacy PLD sockets or direct-solder PCB holes. The supplier device package is 24-PDIP; the 0.100-inch pitch is standard for wire-wrap or point-to-point prototyping boards still used in test jigs and legacy controller repairs.