10 macrocells, 10 ns — the timing and logic budget
The GAL22V10D-10LJ is a 10-macrocell EE PLD from the GAL®22V10 family, with a 10 ns maximum propagation delay (tpd). That 10 ns tpd sets the clock-to-output ceiling for registered logic — combinatorial paths must settle within that window, so the part fits glue-logic applications where the upstream device's output valid window is at least 10 ns wide. The 10 macrocells provide enough fabric to absorb a handful of address decoders, state-machine registers, or bus-arbitration logic without needing a larger device. Each macrocell can be configured as registered or combinatorial, with programmable output polarity — the same flexibility that made the 22V10 architecture a staple for board-level consolidation.
28-PLCC J-Lead — board-fit and thermal interface
Housed in a 28-lead PLCC with J-Leads (28-LCC), the GAL22V10D-10LJ mounts directly to the PCB surface — the J-Lead footprint is 11.51 x 11.51 mm per the supplier device package. The PLCC socket is optional; the J-Lead can be soldered direct for a lower profile than a DIP, though rework requires a hot-air tool rather than a soldering iron.
Obsolete — sourcing reality for the 22V10D-10LJ
Lattice Semiconductor has classified the GAL22V10D-10LJ as obsolete. For existing BOM lines, sourcing runs through independent distribution and surplus channels.