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GAL16V8D-10LJ
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RoHS Compliant · Lead-Free EIA-481 Standard
Lattice Semiconductor Corporation / FPGA / CPLD & Programmable Logic

Lattice GAL16V8D-10LJ EE PLD, 8 Macrocells, 10 ns, 20-PLCC

MPN GAL16V8D-10LJ
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Lattice Semiconductor Corporation GAL®16V8 series EE PLD, 8 macrocells, 10 ns propagation delay, 4.75 V to 5.25 V supply, 20-PLCC (J-Lead) package, commercial temperature range 0°C to 75°C.

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Full Technical Specifications

9 Parameters
GAL16V8D-10LJ specifications
Parameter / AttributeSpecification / Value
SeriesGAL®16V8
MountingSurface Mount
Programmable typeEE PLD
Voltage supply - internal4.75V ~ 5.25V
Operating temperature0°C~75°C(TA)
PackageBulk
Case20-LCC (J-Lead)
Number of macrocells8
Delay time tpd(1) max10 ns
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Technical Details & Description

10 ns speed grade, 8 macrocells — legacy 5 V glue logic

The Lattice GAL16V8D-10LJ is a 10 ns propagation delay EE PLD from the GAL®16V8 family, offering 8 macrocells in a 20-PLCC (J-Lead) package. The 10 ns tpd(1) max means combinatorial inputs propagate to registered outputs within that window — fast enough for most 10-20 MHz bus cycles in older CPLD/FPGA replacement sockets. The 8 macrocells can be configured as registered or combinatorial outputs, giving 16 to 20 usable I/O pins depending on the configuration.

Package and temperature grade for rework and replacement

The J-Lead footprint is common on legacy PLCC sockets and PCB layouts — a direct drop-in for existing GAL16V8 sockets without board spin.

Quantities are lot-specific and confirmed at RFQ.

Frequently asked questions

What is the closest pin-compatible alternative to the GAL16V8D-10LJ?

No pin-compatible direct replacement from Lattice is documented. The GAL16V8D-10LJ is a 5 V, 10 ns, 8-macrocell EE PLD in a 20-PLCC package.

GAL16V8D-10LJ
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