10 ns speed grade, 8 macrocells — legacy 5 V glue logic
The Lattice GAL16V8D-10LJ is a 10 ns propagation delay EE PLD from the GAL®16V8 family, offering 8 macrocells in a 20-PLCC (J-Lead) package. The 10 ns tpd(1) max means combinatorial inputs propagate to registered outputs within that window — fast enough for most 10-20 MHz bus cycles in older CPLD/FPGA replacement sockets. The 8 macrocells can be configured as registered or combinatorial outputs, giving 16 to 20 usable I/O pins depending on the configuration.
Package and temperature grade for rework and replacement
The J-Lead footprint is common on legacy PLCC sockets and PCB layouts — a direct drop-in for existing GAL16V8 sockets without board spin.
Quantities are lot-specific and confirmed at RFQ.