Ethernet PHY for industrial 10/100 links
The ADIN1200CCP32Z is an IEEE 802.3-compliant Ethernet PHY transceiver supporting 10 Mbps and 100 Mbps data rates over twisted-pair or fiber. It operates in full or half duplex and provides MII and RMII interfaces to the MAC layer.
Interface and supply rails
The transceiver integrates four drivers and four receivers, supporting both MII and RMII protocols — RMII halves the pin count to the MAC, freeing GPIO on smaller controllers. Three independent supply domains are required: 1.71V to 1.89V for core, 2.25V to 2.75V for I/O, and 3.14V to 3.46V for the analog PHY. This split-rail architecture isolates digital switching noise from the analog front end.
It is ROHS3 compliant.
Surface-mount assembly is straightforward; the LFCSP requires no special reflow profile beyond typical lead-free solder paste.
