1.5 ns propagation delay — 8-bit transparent latch for low-voltage buses
The Toshiba 74LCX373FT is an 8-bit D-type transparent latch with tri-state outputs, part of the TC74LCX series. The 1.5 ns propagation delay sets the timing margin for the data path — at a 100 MHz bus cycle (10 ns period), 1.5 ns consumes 15% of the cycle, leaving 8.5 ns for setup, hold, and clock-to-output of the driving and receiving devices. This delay is specified at the 1.65 V low end of the supply range; at 3.3 V the delay is typically shorter, but the 1.5 ns max figure is the one to budget in worst-case timing analysis. The tri-state outputs let multiple latches share a common data bus — the high-impedance state eliminates contention when the latch is not selected.
The supplier device package is 20-TSSOP — the same body as the package/case, so the footprint is consistent across the datasheet and the assembly house's library. The 8:8 circuit configuration means eight data inputs map to eight outputs — one independent latch per bit. The single independent circuit confirms that all eight latches share a common enable and output-enable control, simplifying the control logic.
Active lifecycle — sourcing posture
For a low-voltage 8-bit latch in a 20-TSSOP package, the 74LCX373FT is a drop-in candidate for designs using the TC74LCX family.