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Texas Instruments 74F373PC — Discrete Semiconductors

Texas Instruments 74F373PC D-Type Transparent Latch, 8-Bit

MPN74F373PC
End of Life

Texas Instruments 74F series D-Type Transparent Latch, 74F373PC, 8:8 circuit, Tri-State output, 5.3ns propagation delay, 4.5V-5.5V supply, Through Hole 20-DIP (0.300", 7.62mm), 20-PDIP, 0°C-70°C, Active.

$0.49Ref. price · indicative, final on quote
Packaging20-DIP (0.300", 7.62mm)
RoHSRoHS non-compliant
Series74F
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

74F373PC specifications
ParameterValue
Series74F
Logic typeD-Type Transparent Latch
Output typeTri-State
MountingThrough Hole
Voltage4.5V ~ 5.5V
Current - output high, low3mA, 24mA
Operating temperature0°C ~ 70°C
Circuit8:8
PackageBulk
Case20-DIP (0.300\", 7.62mm)
Independent circuits1
Delay time - propagation5.3ns

Product details

8-bit transparent latch with tri-state bus drive

The Texas Instruments 74F373PC is an 8-bit D-type transparent latch with tri-state outputs, part of the 74F fast logic family. It captures data on the D inputs when the latch enable (LE) is high, and holds it when LE goes low — the tri-state outputs then drive or isolate the bus depending on the output enable (OE) state.

With a 5.3 ns max propagation delay from D to Q, this latch keeps up with 74F and 74ALS bus transactions without adding a wait state. The 3 mA source / 24 mA sink output drive gives enough fanout to feed eight 74F-series inputs directly. The commercial temperature grade (0 °C to 70 °C) suits controlled indoor environments; this is not an automotive or extended-industrial part.

20-pin DIP — through-hole board integration

Housed in a 20-pin DIP with 0.300-inch body width, the 74F373PC mounts in standard through-hole sockets or solders directly into plated-through holes. The 20-PDIP footprint is a common 0.100-inch pitch layout — no board respin needed if the existing design already uses a 20-pin DIP latch.

Frequently asked questions

What is the 74F373PC's propagation delay and what does it mean for timing?

The maximum propagation delay from D to Q is 5.3 ns. In a 5 V system running at 25 MHz, this gives roughly 20 ns of setup-and-hold margin after the clock edge — enough for a 74F or 74ALS backplane without adding wait states.

Will 74F373PC drop into a board that was specified around CD74HCT75E?

No — the CD74HCT75E is a 2-bit differential-output latch in a 16-pin DIP. The 74F373PC is an 8-bit tri-state latch in a 20-pin DIP. They are not pin-compatible. A board designed for the 74HCT75 would need a layout change to accommodate the 74F373.