74F00PC — 74F series quad 2-input NAND gate in 14-pin DIP
That 5 ns max delay makes it suitable for high-speed glue logic in legacy 5 V systems where CMOS equivalents like 74HC would introduce 15 ns of propagation delay. Output drive capability is 1 mA sourcing (logic high) and 20 mA sinking (logic low) — the 20 mA sink current handles standard TTL fan-out to ten loads without external buffers.
Active production, RoHS non-compliant — sourcing for legacy BOMs
This part is RoHS non-compliant (lead-bearing), which means it is exempt from RoHS restrictions for certain applications (e.g., aerospace, military, or medical equipment with a legacy exemption).
Temperature grade and environment — commercial range, through-hole package
This suits indoor equipment, benchtop instruments, and telecom racks where the ambient stays within that range. The 14-DIP through-hole package (0.300" row spacing) is a standard breadboard- and protoboard-friendly footprint. No moisture-sensitivity level (MSL) applies to hermetic DIP packages — store on the shelf without dry-pack concerns. Input logic thresholds are TTL-compatible: low at 0.8 V max, high at 2.0 V min. This means it interfaces directly with 5 V TTL outputs (e.g., 74LS, 74S, 74F) without level translation. For 3.3 V logic, a level shifter is required because the 2.0 V VIH(min) exceeds the 3.3 V output's VOH(min) of about 2.4 V.