The Xicor X28C010FM-12 is a 1 Mbit non-volatile parallel EEPROM organized as 128K x 8 bits, with a 120 ns access time and a 4.5 V supply rail. This class of parallel EEPROM is used in embedded systems that require byte- or page-erasable non-volatile storage — firmware parameter tables, calibration constants, configuration maps — where the bus timing must match a legacy microcontroller or FPGA without wait states.
120 ns access — bus timing reality
The 120 ns access time sets the read cycle window for the parallel bus. A microcontroller or CPLD driving the address and control lines must hold the chip select and output enable active long enough for the data to appear on the bus.
Drop-in consideration: X28C513EMB-25
The X28C513EMB-25 is a 512 Kbit parallel EEPROM (half the density) with 150 ns access time, same 4.5 V supply, same 32-PLCC footprint, and same 10 ms write cycle. It is not a direct functional replacement — the memory map is 64K x 8 versus 128K x 8 — but for designs that can tolerate half the storage and a slightly slower read, the pinout and bus protocol are compatible. A firmware change to the upper address decode is required.