100 MHz PLL clock driver with 1:11 fanout
The QS5920AQ is a PLL-based clock driver designed to distribute a single input clock to eleven outputs at up to 100 MHz, targeting SDRAM memory systems that need a clean, low-skew clock tree. It runs from a 3V to 3.6V supply and is specified over the full -40°C to +85°C industrial temperature range, so it fits into telecom, networking, and industrial controller boards that see temperature swings.
Package and integration note
Housed in a 48-pin PDIP (0.600" body width, 15.24 mm row spacing), the QS5920AQ is a through-hole part — it suits prototype runs, rework-friendly designs, or legacy boards where a DIP socket is already on the layout. The differential input and output are both single-ended (No/No), so it accepts and drives standard CMOS/TTL-level clock signals without external termination resistors for a differential pair. With a 1:11 input-to-output ratio, a single QS5920AQ can fan out the system clock to eleven SDRAM devices or DIMM slots, keeping the trace lengths matched and the skew within the PLL's lock range.
Lifecycle and sourcing
Note the RoHS status: marked as non-compliant. If your BOM requires RoHS-10/10 exemption or full lead-free compliance, this part does not carry that cert; check your assembly house's policy on tin-lead DIPs before committing the line. Sourced to order through independent distribution; availability and current pricing are confirmed at RFQ against your target quantity.