PCIe reference clock distribution — 2:12 fanout with integrated PLL
The 9ZML1255AKILF is a zero-delay buffer (Z-BUFFER MUX) that takes a single clock input and distributes it to 12 LP-HCSL outputs, all phase-aligned through the internal PLL. The 2:12 input-to-output ratio means two clock sources can be muxed into the fanout tree — useful for redundant or failover clock architectures on a PCI Express backplane. Rated for 400 MHz maximum frequency with differential I/O on both input and output sides (Yes/Yes), this part sits squarely in the PCIe Gen1 through Gen3 reference clock domain. The LP-HCSL output type is the standard for PCIe clock distribution — no level translation needed between the buffer and the endpoint devices.