PLL clock fanout for server and PCIe clock trees
The 9FG108EGILF is a PLL-based frequency timing generator that takes a single-ended clock or crystal input and produces nine HCSL differential output copies at up to 400 MHz. The 1:9 fanout ratio means one reference oscillator feeds nine PCIe or SATA clock lanes without external buffering.
Differential output architecture
The input accepts either a single-ended clock or a crystal (No/Yes differential), while all nine outputs are HCSL differential pairs. This means the PLL and output drivers handle the single-ended-to-differential conversion on-chip — the layout only needs to route the differential pairs to the PCIe or SATA endpoints, not manage a separate clock conditioner. 400 MHz maximum output frequency covers PCIe Gen1 through Gen3 reference clock requirements (100 MHz multiplied internally), with headroom for higher-speed serial links that need a 400 MHz source.
The tube packaging suits prototyping and low-to-medium volume assembly; for reel quantities, confirm the order code suffix at RFQ.