PCIe signal router — no PLL inside
The Renesas 9DMV0141AKILF is a 2:1 multiplexer for PCI Express reference clock distribution. It takes one of two LVDS input clock sources and routes the selected signal to a single LP-HCSL output. There is no PLL on this die — it is a passive mux, not a clock generator or jitter cleaner. That distinction matters: if your design needs to clean up a noisy clock or synthesize a new frequency, this is not the part. If you need to select between two reference clocks and pass them through with minimal added jitter, this is exactly what it does.
200 MHz ceiling — where it fits
Maximum output frequency is 200 MHz. This covers the PCIe Gen1/Gen2 reference clock domain.
Active, ROHS3, industrial temp
This is not an automotive-grade part (no AEC-Q100), but for the industrial and communications infrastructure it targets, the temperature range is adequate.
Sourcing reality
This is an active, current-production part from Renesas. It is available through the independent distribution channel and can be sourced to order.