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Renesas Electronics 71V3558S166PFG — Memory (DRAM / SRAM / Flash / EEPROM)

71V3558S166PFG ZBT SRAM, 4.5 Mbit, 166 MHz, 3.5 ns

MPN71V3558S166PFG
End of Life

SRAM - Synchronous, SDR (ZBT), 4.5 Mbit, Parallel, 3.5 ns, 166 MHz, 100-LQFP, 3.135V ~ 3.465V, 0°C ~ 70°C.

$4.26Ref. price · indicative, final on quote
Packaging100-LQFP
StockIn Stock (16)
Lead timeIn Stock wk
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
  • MSL-compliant ESD packingMoisture-sealed bags with indicator cards; reels photo-verified.
  • PayPal buyer protectionPay by T/T, PayPal or Payoneer — card payments covered end to end.

Specifications

71V3558S166PFG Technical Specifications
ParameterValue
Memory typeVolatile
Mounting typeSurface Mount
Voltage3.135V ~ 3.465V
Frequency166 MHz
Memory interfaceParallel
Operating temperature0°C ~ 70°C (TA)
PackageBulk
TechnologySRAM - Synchronous, SDR (ZBT)
Access time3.5 ns
Memory size4.5Mbit
Memory formatSRAM
Case100-LQFP
Memory organization256K x 18

Product details

166 MHz clock, 3.5 ns access — the speed-cost tradeoff on a ZBT bus

The 71V3558S166PFG is a 4.5 Mbit synchronous SRAM organised as 256K x 18 bits, clocked at 166 MHz with a 3.5 ns access time. The ZBT (Zero Bus Turnaround) architecture eliminates the dead cycle between read and write on the same port — the bus stays active across direction changes, which matters for shared-memory designs where the controller alternates access every cycle.

The parallel memory interface uses 18 data lines and 18 address lines (256K depth), so the PCB fan-out on a two-layer board is tight; four-layer is the practical minimum for signal integrity at 166 MHz.

Active production — no end-of-life signal

The product status is Active.

Frequently asked questions

What is the memory organisation of 71V3558S166PFG?

The memory is organised as 256K words x 18 bits, giving a total density of 4.5 Mbit. The 18-bit word width (16 data + 2 parity or byte-control bits) is typical for cache-tag or packet-buffer applications.

What package does 71V3558S166PFG use?

The package is surface-mount and RoHS-compliant per the standard lead-free finish.