166 MHz clock, 3.5 ns access — the speed-cost tradeoff on a ZBT bus
The 71V3558S166PFG is a 4.5 Mbit synchronous SRAM organised as 256K x 18 bits, clocked at 166 MHz with a 3.5 ns access time. The ZBT (Zero Bus Turnaround) architecture eliminates the dead cycle between read and write on the same port — the bus stays active across direction changes, which matters for shared-memory designs where the controller alternates access every cycle.
The parallel memory interface uses 18 data lines and 18 address lines (256K depth), so the PCB fan-out on a two-layer board is tight; four-layer is the practical minimum for signal integrity at 166 MHz.
Active production — no end-of-life signal
The product status is Active.
