166 MHz synchronous SRAM with 3.5 ns access
The Renesas 71V3556SA166BGGI is a 4.5 Mbit synchronous SRAM organized as 128K words by 36 bits, clocked at 166 MHz with a 3.5 ns access time. The ZBT (Zero Bus Turnaround) architecture eliminates the dead cycle between read and write operations — the bus stays active every clock edge, which matters when the memory controller is pipelining back-to-back transactions without wait states.
Industrial temperature and supply tolerance
The 119-ball PBGA package (14x22 mm body) routes the 36-bit parallel bus plus address and control signals. The ball pitch and layout are standard for this density class; the PCB fan-out requires at least four layers to escape the inner balls cleanly.
Active production — sourcing posture
Renesas lists the 71V3556SA166BGGI as an active product.