64Kbit parallel SRAM for 8-bit bus designs
The 7164L25YGI is an 8K x 8 asynchronous SRAM organized for direct connection to 8-bit microcontroller and microprocessor buses — no serial bridge or protocol overhead. The 25 ns access time and matching 25 ns write cycle give symmetric read/write timing, so the controller's bus controller can use a single timing parameter for both operations.
28-SOJ footprint and board integration
Housed in a 28-SOJ package with a 0.300-inch (7.62 mm) body width, the 7164L25YGI uses the standard JEDEC SOJ footprint for parallel SRAM — the same land pattern serves many 8K x 8 and 32K x 8 SRAMs in SOJ-28. The surface-mount package suits reflow assembly without through-hole hand-soldering steps. The 64Kbit density fits small lookup tables, calibration constants, boot code shadowing, or data logging buffers where an external serial EEPROM would add latency. For a 5V-only system, this part eliminates the level translator a 3.3V SRAM would require.