Renesas 7130LA25PFGI, 8Kbit (1K x 8) Dual-Port Asynchronous SRAM, 25 ns access time, Parallel interface, 4.5V-5.5V supply, -40°C to 85°C, 64-LQFP (TQFP-64), Tray.
| Parameter | Value |
|---|---|
| Memory type | Volatile |
| Mounting | Surface Mount |
| Supply voltage | 4.5V ~ 5.5V |
| Memory interface | Parallel |
| Operating temperature | -40°C ~ 85°C (TA) |
| Package | Tray |
| Technology | SRAM - Dual Port, Asynchronous |
| Access time | 25 ns |
| Memory size | 8Kbit |
| Memory format | SRAM |
| Case | 64-LQFP |
| Memory organization | 1K x 8 |
| Write cycle time - word, page | 25ns |
The Renesas 7130LA25PFGI is an 8Kbit (organized 1K x 8) dual-port asynchronous SRAM in a 64-TQFP surface-mount package. Its dual-port architecture allows two independent bus masters — two processors, a processor and a DMA controller, or a processor and an FPGA — to read from and write to the same memory array simultaneously without external arbitration logic.
The part ships in Tray — plan for pick-and-place feed accordingly.
The closest functional peer in the same dual-port SRAM family is the 6116SA25SOGI — also 25 ns access time, but 16Kbit (2K x 8) in an SOIC package. The 71321LA20PFG offers 20 ns access time and 16Kbit in a TQFP, but is commercial-temperature (0°C to 70°C) only. Neither is a drop-in replacement; verify footprint, density, and temperature grade before substituting.
Dual-port SRAM provides two independent data/address/control ports, allowing two bus masters to access the same memory array simultaneously. Single-port SRAM has one port and requires external arbitration or a mux if two controllers need to share the memory. For shared-buffer applications (e.g., CPU-to-DSP, FPGA-to-processor), dual-port eliminates the arbitration logic and the associated latency.
Yes, it is certified ROHS3 Compliant.