Altera MAX® 7000A EE PLD, 128 macrocells, 68 I/O, 6 ns tpd(1) max, 3V–3.6V supply, 0°C to 70°C, 84-PLCC package, Bulk.
| Parameter / Attribute | Specification / Value |
|---|---|
| Series | MAX® 7000A |
| Mounting | Surface Mount |
| Programmable type | EE PLD |
| Voltage supply - internal | 3V ~ 3.6V |
| Operating temperature | 0°C ~ 70°C (TA) |
| Package | Bulk |
| Number of i (O) | 68 |
| Case | 84-LCC (J-Lead) |
| Number of gates | 2500 |
| Number of macrocells | 128 |
| Delay time tpd(1) max | 6 ns |
| Number of logic elements (Blocks) | 8 |
Sibling variants, package options, and speed/density grades in this Intel semiconductor series. Active Shenzhen warehouse allocation and rapid 24-48h dispatch.
The Altera EPM7128ALC84-6 is a MAX® 7000A series EE PLD with 128 macrocells, 68 I/O pins, and a 6 ns maximum pin-to-pin delay. It operates from a 3V to 3.6V supply over 0°C to 70°C.
The 3V to 3.6V supply matches LVTTL and LVCMOS I/O standards.
The EPM7128ALC84-6 uses a standard 84-pin PLCC (J-Lead) pinout. The pin assignments for I/O, power, ground, and JTAG are defined in the Altera MAX 7000A datasheet; the 68 I/O pins map to the PLCC-84 footprint.
MAX 7000A devices are in-system programmable via JTAG (IEEE 1149.1) using standard 3.3V logic levels. No external high-voltage programming supply is needed — the core voltage (3V to 3.6V) is sufficient for programming.
The EPM7128ALC84-6 has 68 user I/O pins in the 84-PLCC package.