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Intel EPM570T144A5N — FPGA / CPLD & Programmable Logic
Intel

EPM570T144A5N MAX II CPLD, 440 macrocells, 5.4 ns

MPNEPM570T144A5N
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Altera MAX® II CPLD, EPM570T144A5N, 570 logic elements, 440 macrocells, 5.4 ns tpd, 116 I/O, 144-LQFP, 2.5V/3.3V internal supply, -40°C to 125°C.

$69.0000Ref. price · indicative, final on quote
StockIn Stock (19)
Lead timeIn Stock wk
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
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Specifications

EPM570T144A5N Technical Specifications
ParameterValue
SeriesMAX® II
Mounting typeSurface Mount
Programmable typeIn System Programmable
Voltage supply - internal2.5V, 3.3V
Operating temperature-40°C~125°C(TJ)
PackageTray
Number of i (O)116
Case144-LQFP
Number of macrocells440
Delay time tpd(1) max5.4 ns
Number of logic elements (Blocks)570

Product details

MAX II CPLD – instant-on, low-power glue logic

The Altera EPM570T144A5N is a MAX® II family CPLD with 570 logic elements and 440 macrocells in a 144-LQFP package. The 5.4 ns propagation delay (tpd1) is fast enough for address decoding, bus bridging, and control logic in systems that cannot tolerate the boot-up latency of an FPGA. The MAX II architecture uses a look-up table (LUT) fabric with non-volatile flash configuration, so it powers up ready to drive I/O within microseconds — no external configuration memory needed.

5.4 ns tpd – timing margin for combinatorial paths

The 5.4 ns maximum pin-to-pin delay (tpd1) sets the speed floor for registered and combinatorial logic.

Frequently asked questions

What is the difference between EPM570T144A5N and EPM570T144C5N?

The difference is the temperature grade. The EPM570T144A5N is rated for -40°C to 125°C (industrial/automotive), while the EPM570T144C5N is the commercial-temperature variant (0°C to 70°C). All other specs — logic elements, macrocells, I/O, speed grade, package — are identical.

How to program the EPM570T144A5N with Quartus II?

The EPM570T144A5N is supported in Intel Quartus II software (version 13.0sp1 or later). Use the MAX II device family selection, assign the 144-LQFP package, and program via the JTAG interface using a Byte Blaster II or USB-Blaster cable. The device is in-system programmable and retains configuration in on-chip flash.