128 macrocells, 10 ns pin-to-pin — glue-logic sweet spot
The EPM7128AFC100-10 is a MAX 7000A CPLD with 128 macrocells and a 10 ns maximum pin-to-pin delay (tpd1). That delay defines the combinatorial path ceiling — registered paths clock faster, but any signal crossing through the logic array in one pass is limited to 100 MHz equivalent. For bus-interface decode, address latching, or state-machine encoding, 128 macrocells covers most medium-density glue-logic needs without spilling into a larger device. 84 I/O route through a 100-ball FBGA (11x11 mm). The ball pitch is 1.0 mm — a standard 4-layer board fans out the outer two rows, but the inner balls need at least one buried via or a microvia layer. Plan the BGA escape before committing the layout; the 84 I/O count assumes all balls are usable, but some share with dedicated function pins (JTAG, global clocks, OE).
3.3 V single-rail, EE programmability
No separate VCCIO plane is required for the I/O banks; the same 3.3 V powers the core and the output buffers. The EE PLD cells are in-system programmable via the JTAG interface and retain the configuration on power-off without an external configuration PROM or serial EEPROM. Commercial temperature grade: 0°C to 70°C ambient. This part is specified for indoor, controlled-environment equipment — office peripherals, telecom line cards in conditioned racks, or benchtop instrumentation. Not rated for outdoor, automotive, or industrial enclosures without active cooling.
Active lifecycle, RoHS non-compliant — sourcing note
Because the part is active and RoHS non-compliant, production lots are still being manufactured but the finish limits the addressable market.