Active production, 440 macrocells, 5.4 ns pin-to-pin
The EPM570GT100I5: The 5.4 ns propagation delay (tpd1 max) is the pin-to-pin combinatorial delay at the worst-case corner — it governs the clock-to-output path and the setup margin for any registered input.
I/O budget and supply rails
76 user I/O pins are available in the 100-TQFP package. The core runs from 1.71 V to 1.89 V (1.8 V nominal) — a single 1.8 V rail powers the logic array and the in-system programming controller. The I/O banks operate at the same 1.8 V level, so level translation is needed when interfacing to 3.3 V peripherals.
Sourcing and supply posture
The MAX II family uses a 1.8 V flash-based fabric that retains the configuration on power-off — no external configuration memory or boot-up delay. The in-system programmable (ISP) interface supports JTAG programming via a standard 10-pin header, and the 440 macrocells are sufficient for address decoding, state machines, and bus arbitration in a typical industrial control card.