MAX II CPLD – 570 logic elements, 440 macrocells in a 100-TQFP
The Intel EPM570GT100C4 is a MAX II family CPLD packing 570 logic elements and 440 macrocells in a 100-TQFP (14x14 mm) surface-mount package. It provides 76 user I/O and a maximum propagation delay (tpd1) of 5.4 ns.
5.4 ns tpd – what it buys you on the bus
The 5.4 ns pin-to-pin delay means this CPLD can sit between a fast SRAM and a 100 MHz-class processor without adding a wait state. For address decoding or control-signal generation, that timing headroom keeps the critical path clean. If your design needs faster combinational logic, the MAX 7000B series offers 4 ns parts (e.g., EPM7128BUC169-4), but those parts run on a 2.375 V core and pack only 128 macrocells – a different density tier.