MAX II CPLD — 440 macrocells, 160 I/O, 5.4 ns pin-to-pin
The Intel EPM570GF256C5 is a MAX® II family CPLD with 440 macrocells and 570 logic elements, packaged in a 256-ball FBGA (17x17 mm) for surface-mount assembly. It provides 160 user I/Os and a pin-to-pin propagation delay (tpd1) of 5.4 ns maximum, making it suitable for board-level glue logic, address decoding, and state-machine control in commercial-temperature equipment (0°C to 85°C). The device is in-system programmable via JTAG, so firmware updates or logic changes can be applied on the assembled board without a separate programmer.
