The Intel EPM570GF100C5N is a MAX® II family CPLD packing 440 macrocells and 570 logic elements into a 100-ball FBGA (11x11 mm). It gives you 76 user I/O, in-system programmability via JTAG, and a 5.4 ns pin-to-pin delay — fast enough for address decoding, bus bridging, and control logic in telecom line cards, base station backplanes, and industrial controller I/O modules where the ambient temperature stays within 0°C to 85°C.
Supply and temperature — design constraints
Core voltage is 1.71 V to 1.89 V.