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Infineon Technologies CY7C1441KV33-133AXI — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon CY7C1441KV33-133AXI 36Mbit Sync SRAM, 133 MHz

MPNCY7C1441KV33-133AXI
Active

Infineon Technologies CY7C1441KV33-133AXI synchronous SDR SRAM, 36Mbit, 133 MHz clock, 6.5 ns access time, 1M x 36 organization, 100-TQFP, tray.

$64.4600Ref. price · indicative, final on quote
Infineon Technologies CY7C1441KV33-133AXI datasheet (PDF)
Packaging100-LQFP
RoHSROHS3 Compliant
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

CY7C1441KV33-133AXI specifications
ParameterValue
Memory typeVolatile
MountingSurface Mount
Voltage3.135V ~ 3.6V
Frequency133 MHz
Memory interfaceParallel
Operating temperature-40°C ~ 85°C (TA)
PackageTray
TechnologySRAM - Synchronous, SDR
Access time6.5 ns
Memory size36Mbit
Memory formatSRAM
Case100-LQFP
Memory organization1M x 36

Product details

36Mbit synchronous SDR SRAM at 133 MHz

The CY7C1441KV33-133AXI: This is a single-data-rate (SDR) pipeline part — each rising clock edge latches the address and returns data on the next edge, making it a fit for high-throughput cache or buffer memory in networking, telecom, and industrial control backplanes where deterministic read latency matters more than double-data-rate bandwidth.

100-TQFP footprint and tray delivery

Supplied in tray format, which is the standard handling medium for low-to-medium volume production and prototype builds; no reel taping, so pick-and-place feeders need a tray shuttle.

Active lifecycle and sourcing posture

No pin-compatible second-source is listed on the official record, so the BOM line is single-sourced to this Infineon order code.

Frequently asked questions

Is CY7C1441KV33-133AXI obsolete?

No — it carries an Active lifecycle status from Infineon.

What is the memory organization of CY7C1441KV33-133AXI?

Organized as 1M words by 36 bits (1M x 36), for a total of 36 Mbit. The 36-bit word width maps naturally to a 32-bit data bus plus 4 parity/ECC bits, or to a 36-bit DSP data path without byte packing.

What is the access time and clock speed?

Rated for a 133 MHz clock with a 6.5 ns access time. The 6.5 ns figure is the time from clock edge to valid data out — it sets the setup/hold margin at the receiving device on a 133 MHz bus.