36Mbit synchronous SDR SRAM at 133 MHz
The CY7C1441KV33-133AXI: This is a single-data-rate (SDR) pipeline part — each rising clock edge latches the address and returns data on the next edge, making it a fit for high-throughput cache or buffer memory in networking, telecom, and industrial control backplanes where deterministic read latency matters more than double-data-rate bandwidth.
100-TQFP footprint and tray delivery
Supplied in tray format, which is the standard handling medium for low-to-medium volume production and prototype builds; no reel taping, so pick-and-place feeders need a tray shuttle.
Active lifecycle and sourcing posture
No pin-compatible second-source is listed on the official record, so the BOM line is single-sourced to this Infineon order code.