18 Mbit synchronous SDR SRAM — 167 MHz, 512K x 36, 100-TQFP
The Infineon CY7C1380KV33-167AXI is an 18 Mbit synchronous SDR (single data rate) SRAM organized as 512K words by 36 bits. It clocks at 167 MHz and delivers a 3.4 ns access time — the window between the clock edge and valid data on the bus. At 167 MHz, the 3.4 ns access time leaves roughly 2.6 ns of the 6 ns clock period for the output hold and the downstream FPGA or ASIC's input setup — a timing margin that matters when the trace length exceeds 50 mm on a standard FR4 board. The 36-bit data bus is typical for networking or telecom packet buffers where the parity or ECC bits run alongside the 32-bit word.
Supply voltage and temperature grade — the exact operating envelope
A 3.3 V regulator with ±2 % tolerance stays inside this window, but a 3.3 V rail that dips to 3.0 V during a transient is out of spec and risks data corruption on a read cycle.
Active lifecycle and compliance — no PCN watch needed
The base product number is CY7C1380; the -167AXI suffix encodes the 167 MHz speed grade, the AXI industrial-temperature Tray variant. The commercial-temperature sibling (CY7C1380KV33-167AXC, 0°C to 70°C) is a drop-in for indoor-only builds — same footprint, same timing, different temperature bin.