9 Mbit synchronous pipeline for high-throughput buffering
The CY7C1360C-200AXC is a 9 Mbit synchronous SRAM organized 256K x 36, clocked at 200 MHz with a 3 ns access time. The 36-bit word width suits systems that move data in wide bursts — network packet buffers, DSP coefficient stores, or cache tag RAMs where a single read cycle delivers a full cache line or descriptor. The parallel memory interface and synchronous SDR pipeline mean the address is latched on the rising clock edge; the data appears after the pipeline latency, not after a random access time.
Package, footprint, and assembly profile
Supplied in a 100-LQFP (100-TQFP, 14x20 mm body) on Tray.
Lifecycle and supply posture
Listed as Active in production with ROHS3 compliance. Sourced through authorized and independent distribution; lead time and pricing confirmed at RFQ against the BOM quantity.
How the 256K x 36 organization compares to a 512K x 18 sibling
The closest peer in density is the CY7C1356C-250AXC — same 9 Mbit frame, same 100-TQFP footprint, same supply and temperature grade. The CY7C1356C organizes the memory as 512K x 18 (half the word width, double the depth) and clocks at 250 MHz with a 2.8 ns access time. The choice between the two is a bus-width decision: the CY7C1360C delivers 36 bits per cycle for a wide datapath; the CY7C1356C trades width for depth and a higher clock ceiling.