Infineon CY7C1021DV33-10ZSXI, 1Mbit asynchronous SRAM, 10 ns access time, 64K x 16 organization, 3.0-3.6V supply, -40 to 85°C industrial temperature, 44-TSOP II package, Tray.
| Parameter / Attribute | Specification / Value |
|---|---|
| Memory type | Volatile |
| Mounting | Surface Mount |
| Supply voltage | 3V ~ 3.6V |
| Memory interface | Parallel |
| Operating temperature | -40°C~85°C(TA) |
| Package | Tray |
| Technology | SRAM - Asynchronous |
| Access time | 10 ns |
| Memory size | 1Mbit |
| Memory format | SRAM |
| Case | 44-TSOP (0.400\", 10.16mm Width) |
| Memory organization | 64K x 16 |
| Write cycle time - word, page | 10ns |
Factory lead times blocking production? We lock verified brand-new original stock in Shenzhen within 2 hours.
Direct access to Shenzhen floor inventory, franchised allocation buffers, and factory bonded stock to resolve line-down shutdowns.
Standard factory-sealed packaging compliant with EIA-481 standards for automated high-speed SMT pick-and-place lines.
High-resolution photos of original reel labels, 2D DataMatrix, and pin coplanarity sent via WhatsApp/Telegram before you release wire payment.
The Infineon CY7C1021DV33-10ZSXI is a 1Mbit asynchronous SRAM organized as 64K x 16 bits, with a 10 ns access time and a parallel interface. It operates from a 3.0V to 3.6V supply, making it a direct fit for 3.3V logic systems.
The 10 ns access time and 10 ns write cycle time set the window for address-to-data valid and write strobe timing.
It is a 1Mbit asynchronous SRAM with 64K x 16 organization, 10 ns access time, 3.0V to 3.6V supply, -40°C to 85°C industrial temperature range, and a parallel interface in a 44-TSOP II package.
This part is available to order through independent distribution. Pricing and current stock levels are confirmed at quote time against an RFQ — submit a request for a firm quote with lead time.
The 'I' in the suffix denotes industrial temperature range; the 'X' in the package code indicates RoHS compliance per Infineon's standard part-numbering convention.
The access time is 10 ns for both read and write cycles.
Yes, it is an asynchronous SRAM — no clock input required. Address changes directly enable data output after the access time.