133.33 MHz PLL clock source with bypass — BOM-fit note
The CY26580OI-1 is a PacketClock™ clock generator that also integrates fanout distribution and a multiplexer in a single 20-SSOP package. Its maximum output frequency of 133.33 MHz sets the clock ceiling for the target interface — typically a SONET/SDH or Ethernet framer that needs a clean reference at that rate. The on-chip PLL includes a bypass mode (: PLL Yes with Bypass), meaning the reference clock can pass through unmodified when the system needs a jitter-free path or during board-level debug. Input and output are both single-ended CMOS, not differential — the fanout stays within a single board, not a backplane. The industrial temperature range (-40°C to 85°C,) suits outdoor telecom cabinets or factory-floor controllers where ambient heat cycles are the norm.
Package and supply integration
The supplier device package is listed as 20-QSOP — the QSOP variant shares the same footprint but has a thinner body; both are surface-mount and reflow-compatible. Single PLL circuit with a 1:2 input-to-output ratio — one reference clock drives two output trees. The divider/multiplier block is present (Yes/No,), so the PLL can multiply the reference up to the 133.33 MHz ceiling or divide it down for lower-speed domains.