AEC-Q100 NOR gate for the engine bay
The SN74AHC02QPWRG4Q1: It packs four independent NOR gates into a 14-TSSOP package, each with two inputs and a standard push-pull output rated for 8mA source and sink. The supply range spans 2V to 5.5V. Quiescent current maxes at 2 µA.
7.5ns propagation delay — timing margin at speed
The maximum propagation delay is 7.5ns at 5V with a 50pF load. That 7.5ns ceiling defines the timing budget for the NOR gate in a high-speed control path — for example, gating a PWM enable signal or combining sensor fault flags. At 3.3V the delay will be slightly longer (the 74AHC family typically adds ~2ns when dropping from 5V to 3.3V), so budget accordingly if the rail is below 5V. The 8mA symmetric output drive handles standard CMOS fan-out to four or five downstream gate inputs without signal degradation.
14-TSSOP: standard footprint, MSL expectations
The 14-TSSOP package with 0.173" body width and 4.40mm width is a mainstream logic footprint. It places cleanly on standard pick-and-place equipment and is widely second-sourced across the 74AHC family.