Dual-rail supervisor for PCI local-bus sequencing
The LMC6953CM/NOPB: The open-drain output lets multiple supervisors share a common pull-up resistor on a shared reset bus, which is standard practice in PCI local-bus systems where the power-up sequence must hold the bus devices in reset until both rails are stable. The 100ms minimum reset timeout gives the power supplies time to ramp and the oscillator to stabilize before the processor starts executing code. This is longer than a simple power-on reset IC and suits systems with slow-starting regulators or large bulk capacitance on the output.
The 8-SOIC package (3.90mm width) is a standard JEDEC footprint — the same land pattern used by countless other supervisors, op-amps, and interface ICs — so no board respin is needed if you swap from another 8-pin SOIC supervisor. Surface-mount assembly with the SOIC-8 body suits reflow soldering. The package is moisture-sensitive per J-STD-020; the floor life classification is not listed here, so standard MSL handling applies unless the reel label specifies otherwise.