Regulator identity and key parametrics
The STMicroelectronics LDCL015MR is a single-output, positive adjustable LDO rated for 150 mA continuous output. It regulates down to a 0.8 V minimum output, with a maximum of 5.4 V, from an input rail up to 5.5 V. Dropout voltage is 0.1 V maximum at 100 mA load — the headroom between the input rail and the regulated output must stay above this figure across the full load range to maintain regulation. The 160 µA quiescent current makes it a candidate for always-on rails in battery-powered designs where the regulator's own draw is part of the sleep budget. The SOT-23-5 package (SC-74A, SOT-753) uses a standard 5-pin land pattern compatible with lead-free reflow profiles.
PSRR across frequency — what the band tells you
Power-supply rejection ratio is specified at 52 dB at 1 kHz, rolling to 51 dB at 10 kHz. This 1 dB droop across a decade means the regulator attenuates 100 kHz switching noise by roughly 30 dB less than it does at 1 kHz — upstream buck converter ripple above the crossover frequency will pass through unless filtered ahead of the LDO. For a 1.8 V rail feeding a sensitive analog front-end, the PSRR at 10 kHz determines how much of a 400 kHz switching ripple couples into the output. A 50 mVpp ripple at 10 kHz is suppressed to roughly 0.14 mVpp — acceptable for a 12-bit ADC reference but marginal for a 16-bit or higher-resolution chain.
Protection set and control interface
The LDCL015MR integrates over-current, over-temperature, and short-circuit protection. The OCP threshold triggers before the pass element enters its secondary-breakdown region; the OTP shutdown activates at a die temperature above the 125°C rated maximum, protecting against sustained thermal runaway. An Enable pin (active-high logic) allows the output to be gated by a GPIO or a power-good supervisor.