Synchronous burst SRAM for pipelined processor caches
The MT58L128L18PT-10 is a 2 Mbit synchronous burst SRAM from Micron's SYNCBURST family, organized 128K x 18. The 18-bit word width accommodates a parity or ECC check bit alongside a 16-bit data word — useful in cache or buffer applications where data integrity is tracked per word. Rated for a 100 MHz clock and a 5 ns access time, this part is designed to feed a pipelined processor or DSP with a deterministic read latency. The 5 ns access is the time from address assertion to valid data on the bus at the rated supply and temperature; the actual system timing budget must include the board trace delay and the input capacitance of the receiving device.
Housed in a 100-lead TQFP (14x20.1 mm body), the MT58L128L18PT-10 uses a fine-pitch gull-wing lead form. Marked as RoHS non-compliant, this part likely carries a tin-lead (SnPb) finish on the leads. For legacy BOMs that require a lead-bearing solder joint, this is a direct fit; for RoHS-mandated assemblies, verify the exemption or plan for a lead-free alternative.