Triple PLL for Ethernet and wireless base-station timing
The Microchip ZL30793LFG7 is a triple-channel 1588 timing card PLL for Ethernet, SONET/SDH, and wireless base-station applications. It integrates three PLL circuits in an 80-LGA package, accepting five CMOS inputs and delivering ten outputs configurable as CMOS, HCSL, HSTL, LVDS, or LVPECL. The 1.045 GHz maximum output frequency covers the fastest SERDES reference clocks used in 10G/25G/100G line cards and baseband processing chains.
The 1.045 GHz max frequency means this PLL can directly clock the high-speed serial transceivers on an FPGA or ASIC without an external frequency doubler. In practice, the usable output frequency depends on the selected standard — LVDS and LVPECL paths will reach that ceiling; CMOS outputs are typically limited to lower frequencies due to single-ended drive constraints. The differential input and output capability (Yes/Yes per the spec) ensures signal integrity at these speeds over the 11x11 mm LGA footprint.
Supply rails and temperature range
The part is ROHS3 compliant.