109000 logic elements — the gate budget you actually route
The MPF100T-FCSG325I is a Microchip PolarFire FPGA with 109000 logic elements and 7782400 total RAM bits, giving you a 109K LE gate array plus 7.6 Mbits of on-chip block memory. The 170 user I/O are distributed across a 325-ball BGA package, surface-mount only.
0.97 V core rail — plan the PDN before you route
The 0.97 V core supply is a tight-tolerance rail. A standard 1.0 V regulator with ±5 % output sits at 0.95 V to 1.05 V — the low end is below the core minimum. You need a regulator with adjustable output or a 0.97 V fixed part, and the decoupling cap plan must keep the transient below 30 mV. The 325-ball BGA has a 1.0 mm pitch; route the core power on inner layers with a solid plane, not a star trace.
For a new design, this part does not force an early migration plan — you can commit the BOM line without an obsolescence contingency.
170 I/O — what the pin count buys you
The 170 I/O are multiplexed across the PolarFire fabric. Each I/O bank can be configured for single-ended standards (LVCMOS, LVTTL, SSTL) or differential pairs (LVDS, LVPECL). The 325-ball BGA gives you enough package pins to bring out most of the I/O, but the exact usable count depends on the bank voltage assignments and the differential-pair pairing rules in the Libero SoC place-and-route tool.