Four 100k pots, 129 taps each, SPI-bussed
The MCP4341-104E/ML packs four independent 100 kΩ digital potentiometers into a single 20-QFN package, each with 129 wiper taps and a linear taper. The SPI interface lets you daisy-chain multiple devices or share a bus with other SPI peripherals — one chip-select line per device, or a single CS with daisy-chain mode. Non-volatile memory (WiperLock™ technology) stores the wiper position when power is removed, so the divider ratio comes up at the last programmed value on next power-on — no host re-initialization needed after a brownout or power cycle.
129-tap resolution and the so-what for your divider
129 taps across a 100 kΩ end-to-end resistance gives a step size of roughly 781 Ω per tap (100 kΩ / 128 steps). For a voltage divider, that is about 0.78 % of the supply per step — fine enough for bias trimming, gain setting, or offset nulling in analog signal chains where a 1 % resistor tolerance would be the limiting factor, not the pot resolution. The wiper resistance is 75 Ω typical, which adds a small series offset at the wiper node. In a voltage-divider configuration the wiper resistance sees only the load current, so the error is negligible for high-impedance loads — but if you are driving a low-impedance input directly, the 75 Ω forms a voltage divider with the load and shifts the output. Temperature coefficient is 150 ppm/°C typical. Over the full -40 to +125 °C range, the 100 kΩ end-to-end drifts by about ±1.2 kΩ worst-case — the divider ratio stays tighter because both halves of the resistor string track each other.
Supply rails and temperature grade
The 20-VFQFN package with exposed pad needs a thermal via array under the paddle to pull heat into the PCB ground plane — the datasheet's recommended footprint is 4x4 mm with the pad soldered to a copper island. Without that, the junction temperature rise at 5.5 V and maximum wiper current will exceed the 125 °C limit in still air.