Microchip no longer manufactures this specific speed grade and package variant. Any remaining stock in the channel is last-time-buy or surplus inventory.
10 ns speed — timing margin in a 5V PLD
This is a 10 ns propagation delay part from the 22V10 family of EE PLDs. The 10 ns speed grade means the combinatorial path from input through the AND/OR array to the registered output settles within 10 ns, which sets the system clock ceiling. For a 5V-only logic bus, that timing budget is tight enough for 50-80 MHz state machines depending on the feedback path.
10 macrocells in a 28-PLCC footprint
The device provides 10 macrocells, each configurable as registered or combinatorial output. The 28-PLCC (J-Lead) package measures 11.51 x 11.51 mm and is surface-mount. The 5V-only supply rail is fixed — no mixed-voltage core/I/O support.
We source it through independent and surplus supply lines.