Obsolete — plan the replacement now
That means no further factory orders — the only channel is surplus or broker stock, sourced per RFQ.
15 ns — timing budget for glue logic
This is a 15 ns EE PLD from the 16V8 family, packing 8 macrocells and running on a single 5 V rail. The 15 ns propagation delay sets the combinational-logic timing floor — it replaces 74-series TTL or older PAL parts in address decoding, state machines, or bus-interface logic where the clock period is above ~30 ns.
20-TSSOP — field-swap reality
The 20-TSSOP package (0.173" body width, 4.40 mm) is a fine-pitch surface-mount part. No lab bench? You will need a hot-air station with a fine nozzle and a steady hand — not a soldering-iron swap. The 0.65 mm pitch means the orientation mark (pin 1 dot) is small; check it under magnification before placing.
What fits in 8 macrocells
Eight macrocells — each can be configured as a registered or combinatorial output. That is enough for a small address decoder, a 4-bit counter, or a handful of state bits. If your design needs more than that, you are looking at the wrong density tier.