It is not available through the factory channel, and no official successor order code has been published for this exact configuration. For production or repair programs that require this exact part number, sourcing runs through independent distribution.
15 ns propagation delay — timing budget for glue logic
The 15 ns propagation delay is the pin-to-pin combinatorial delay through the PLD at 5 V supply and 25 °C. This sets the maximum clock rate for registered logic and the signal settling time for combinatorial decode paths. A replacement must match or beat this delay to avoid violating existing setup/hold margins on the board.
8 macrocells and 5 V supply — legacy logic density
Eight macrocells provide up to eight registered outputs or combinatorial logic terms — typical for address decoding, bus arbitration, or state-machine replacement in 5 V systems. The 5 V supply rail is fixed; this part does not operate at 3.3 V or lower. Any drop-in substitute must also be a 5 V device.
20-SOIC wide-body footprint — board-level constraint
This is not the same footprint as the narrow 20-SOIC (typically 0.208" / 5.30 mm body). A replacement must be offered in the wide-body SOIC-20 to fit the existing PCB layout without a board spin.