32-PLCC footprint and board integration
The AT28HC256F-90JU-T comes in a 32-lead PLCC (J-Lead) package, supplier device package 32-PLCC measuring 13.97x11.43 mm. The J-lead footprint allows socketed or soldered mounting on surface-mount boards, with the leads tucked under the body to save real estate compared to a SOIC of the same pin count.
90 ns access — what it means for read timing
With a 90 ns access time, the AT28HC256F-90JU-T delivers data to the bus within 90 ns of the address being valid. This is fast enough to interface with most 8-bit microcontrollers and CPLDs running at clock rates up to roughly 10 MHz without inserting wait states, depending on the controller's memory-cycle timing. The memory is organized as 32K x 8 bits (256 Kbit total), addressed via a 15-bit parallel address bus, with chip-enable and output-enable controls for bus sharing.
Industrial temperature grade and write endurance
The write cycle time is 10 ms per word or page — typical for parallel EEPROMs of this density — and the device supports byte and page write modes for firmware parameter storage.