64 Mbit SPI NOR flash for code storage and fast boot
It communicates over a SPI bus with Quad I/O and QPI support, clocking at 108 MHz.
The 108 MHz clock rate with Quad I/O delivers effective read bandwidth well above single-bit SPI at the same frequency. In a typical Cortex-M design that shadows code from flash to SRAM at boot, this part cuts the transfer window compared to a single-SPI part.
Package and mounting: 8-WSON with exposed pad
The exposed pad is typically tied to ground. The tape-and-reel variant (TR suffix) is the standard ordering option for automated pick-and-place; the cut-tape option suits prototype or low-volume builds.
