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Infineon Technologies S29GL01GT11FHV010 — Memory (DRAM / SRAM / Flash / EEPROM)

Infineon S29GL01GT11FHV010 1Gbit Parallel Flash, 110ns

MPNS29GL01GT11FHV010
Active

Infineon Technologies GL-T series Parallel NOR Flash, S29GL01GT11FHV010, 1Gbit, 128M x 8, 110 ns access, 2.7 V, -40 to +105°C, 64-FBGA, Tray.

$12.01Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

S29GL01GT11FHV010 specifications
ParameterValue
SeriesGL-T
InterfaceParallel
MountingSurface Mount
Operating temperature high-40°C to 105°C (TA)
Frame_size1Gbit
Access time110 ns
Memory typeNon-Volatile
Package_typeTray
Memory formatFLASH
StatusActive
Supply voltage2.7
Memory organization128M x 8
Write cycle time - word, page60ns

Product details

1 Gbit parallel NOR Flash for code-shadowing and data-logging

The Infineon S29GL01GT11FHV010 is a 1 Gbit parallel NOR Flash memory from the GL-T series, organized as 128M x 8 bits. This density suits firmware storage for embedded systems requiring fast random-read performance — NOR Flash supports execute-in-place (XIP) code shadowing, eliminating the need to copy code to RAM before execution. The 110 ns access time means the processor's memory controller can read the first instruction within a single bus cycle at typical embedded clock rates.

Active production with industrial temperature qualification

The 2.7 V supply rail allows operation from a 3.3 V bus with margin for brownout conditions, or from a regulated 2.8 V rail in low-power designs. The parallel interface provides deterministic read timing without the protocol overhead of serial Flash — important for real-time boot sequences where every microsecond of latency matters.

64-ball FBGA footprint and board integration

Supplied in a 64-ball FBGA package on tray, surface-mount.

Frequently asked questions

What is the S29GL01GT11FHV010's memory organization and access time?

It is organized as 128M x 8 bits (1 Gbit total) with a 110 ns initial access time and a 60 ns write cycle time for word and page operations. The parallel interface provides deterministic read latency suitable for code shadowing and real-time boot applications.