PSoC 5 at 67 MHz — what the core speed buys you
Memory budget: 128 KB Flash, 32 KB SRAM, 2 KB EEPROM
Program memory is 128 KB Flash, backed by 32 KB SRAM and a separate 2 KB EEPROM block.
Supply range and power tree simplification
Peripheral integration: CapSense, USB, LCD, and more
On-chip CapSense eliminates a dedicated touch controller for up to 38 capacitive-sensing channels. The USB interface (full-speed device) handles HID or CDC class connections without an external PHY. LCD drive supports direct segment LCD panel connection, saving a driver IC. DMA offloads data movement between peripherals and memory. These integrated blocks reduce BOM count and board area significantly compared to a discrete MCU + touch + USB + LCD driver solution.
For volume production, this part can be sourced through independent channels against an RFQ.
