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Infineon Technologies CY7C1373D-100AXC — Memory (DRAM / SRAM / Flash / EEPROM)

Cypress CY7C1373D-100AXC 18Mbit NoBL SRAM, 100 MHz, 8.5 ns

MPNCY7C1373D-100AXC
Obsolete

Cypress NoBL™ synchronous SRAM, CY7C1373D-100AXC, 18Mbit organized 1M x 18, 100 MHz clock, 8.5 ns access time, 3.3 V supply, 100-LQFP, 0°C to 70°C commercial temperature.

Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Jul 2026

Specifications

CY7C1373D-100AXC specifications
ParameterValue
SeriesNoBL™
Memory typeVolatile
MountingSurface Mount
Supply voltage3.135V ~ 3.6V
Clock frequency100 MHz
Memory interfaceParallel
Operating temperature0°C~70°C(TA)
PackageTray
TechnologySRAM - Synchronous, SDR
Access time8.5 ns
Memory size18Mbit
Memory formatSRAM
Case100-LQFP
Memory organization1M x 18

Product details

18 Mbit NoBL synchronous SRAM — what this part does

The Cypress CY7C1373D-100AXC is an 18 Mbit synchronous SRAM from the NoBL family, organized 1M x 18. It operates from a 3.135 V to 3.6 V supply with a 100 MHz clock and delivers an 8.5 ns access time.

Obsolete — sourcing reality and what replaces it

The product record notes no documented successor — there is no official drop-in replacement from Cypress. For a BOM line that must stay at this density and speed, the procurement path is surplus and broker channels. If your design is still in development, consider evaluating a current-production synchronous SRAM in the same package footprint to avoid future obsolescence-driven redesigns.

Frequently asked questions

What is the closest pin-compatible alternative to CY7C1373D-100AXC?

Cypress does not document a direct successor for this part. For a current-production alternative, evaluate other 100-pin LQFP synchronous SRAMs with 1M x 18 organization and 100 MHz clock — pin compatibility must be verified against the target device datasheet.

What is CY7C1373D-100AXC's listed series?

It belongs to the Cypress NoBL (No Bus Latency) family of synchronous SRAMs, which eliminates dead cycles between read and write bus turns.